ISL6112INZA-T【PDF 5/30 页】IC PWR CNTRLR DUAL SLT 48-TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录38

1页 2页 3页 4页 [5页]6页 7页 8页 9页

ISL6112

FN6456.1

August 25, 2011

14, 23 3VGATEA 3VGATEB 3V gate drive outputs. Each pin connects to the gate of an external N-Channel MOSFET. During power-up, the

CGATE and the CGS of the MOSFETs are connected to a 25礎 current source. This controls the value of dv/dt

seen at the source of the MOSFETs, and hence the current flowing into the load capacitance. During current

limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of

FLT

. Whenever an overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the GATE pin

for the affected slot is immediately brought low. During power-down, these pins are discharged by an internal

current source.

11, 26 VSTBYA, VSTBYB 3.3V standby input voltage. Required to support PCI-Express VAUX output. Additionally, the SMBus logic and

internal registers run off of V

STBY

to ensure that the chip is accessible during standby modes. A UVLO circuit

prevents turn-on of this supply until V

STBY

rises above its UVLO threshold. Both pins must be externally

connected together at the ISL6112 controller.

15, 22

VAUXA, VAUXB 3.3VAUX outputs to PCI-Express card slots. These outputs connect the 3.3AUX pin of the PCI-Express

connectors to V

STBY

via internal 400m?MOSFETs. These outputs are 1A current limited and protected

against short-circuit faults.

44, 43

ONA, ONB Enable inputs. Rising-edge triggered. Used to enable or disable the MAINA and MAINB (+3.3V and +12V)

outputs. Taking ON low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie these

pins to GND if using SMI power control. Also see pin descriptions for FAULT

A and FAULT

45, 42 AUXENA, AUXENB Level sensitive auxiliary enable inputs. Used to enable or disable the VAUX outputs. Taking AUXEN low after a

fault resets the respective slots Aux Output Fault Latch. Tie these pins to GND if using SMI power control. Also

see pin descriptions for FAULT

A and FAULT

2, 35 CFILTERA, CFILTERB Overcurrent timers. Capacitors connected between these pins and GND set the duration of CR

TIM

. CR

TIM

the amount of time for which a slot remains in current limit before its isolation protection is invoked.

6, 31 PWRGD

A PWRGD

B Power-is-Good outputs. Open-drain, active-low. Asserted when a slot has been commanded to turn on and has

successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an

external pull-up resistor to V

STBY

1, 36

FAULT

A, FAULT

B Fault outputs. Open-drain, active-low. Asserted whenever the isolation protection trips due to a fault condition

(overcurrent, input undervoltage, over-temperature). Each pin requires an external pull-up resistor to V

STBY

Bringing the slots ON pin low resets FAULT

, if FAULT

was asserted in response to a fault condition on one of

the slots MAIN outputs (+12V or +3.3V). FAULT

is reset by bringing the slots AUXEN pin low if FAULT

was

asserted in response to a fault condition on the slots VAUX output. If a fault condition occurred on both the

MAIN and VAUX outputs of the same slot, then both ON and AUXEN must be brought low to de-assert the FAULT

output.

9, 28

FORCE_ON

Enable inputs. Active-low, level-sensitive. Asserting a FORCE_ON

input turns on all three of the respective

slots outputs (+12V, +3.3V, and VAUX) while specifically defeating all protections on those supplies. This

explicitly includes all overcurrent and short-circuit protections, and on-chip thermal protection for the VAUX

supplies. Additionally included are the UVLO protections for the +3.3V and +12VMAIN supplies. The

FORCE_ON

pins do not disable UVLO protection for the VAUX supplies. These input pins are intended for

diagnostic purposes only. Asserting FORCE_ON

causes the respective slots PWRGD

and FAULT

pins to enter

their open-drain state. Note that the SMBus register set continues to reflect the actual state of each slots

supplies. There is a pair of register bits, accessible via the SMBus, which can be set to disable (unconditionally

de-assert) either or both of the FORCE_ON

pins; see CNTRL Register Bit D[2].

4, 38

GPI_A0, GPI_B0 General purpose inputs. The states of these two inputs are available by reading the Common Status Register,

Bits [4:5]. If not used, connect each pin to GND.

39, 40, 41

A2, A1, A0 SMBus address select pins. Connect to ground or leave open in order to program device SMBus base address.

These inputs have internal pull-up resistors to V

STBY

. Address programmed on rising V

STBY

SDA

Bidirectional SMBus data line.

SCL

SMBus clock input.

INT

Interrupt output. Open-drain, active-low output. Asserted whenever a power fault is detected if the INTMSK bit

(CS Register Bit D[3]) is a logical 0. This output is cleared by performing an echo reset to the appropriate

fault bits in the STAT or CS registers. This pin requires an external pull-up resistor to V

STBY

17, 33, 46

GND IC reference pins. Connect together and tie directly to the systems analog GND plane directly at the device.

7, 18, 19, 20, 30

Reserved. Make no external connections to these pins.

Pin Descriptions (Continued)

PIN NUMBER PIN NAME

PIN FUNCTION

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式